1. Field of the Invention
The present invention relates generally to methods of semiconductor manufacture and, more particularly, to enhancing the fill-in of inter-layer dielectric material.
2. Description of Related Art
Multi-layered state-of-the-art microchips require fill-in of an inter-layer dielectric (ILD) to isolate transistors of one layer from transistors of another. As geometries become smaller, e.g. in chips having critical dimensions in a sub-3x nm (i.e., sub 30 nm) range, ILD fill-in may include, undesirably, voids that may result in leaking of electrical current between adjacent transistors. Key steps in the ILD fill-in process involve depositing layered materials on a substrate, e.g., silicon, and etching to form a pattern of transistors, e.g., having polysilicon (PL) gates, and depositing insulating material (e.g., oxide) to create an inter-layer dielectric. When oxide fill-in is incomplete, the required isolation between transistors may not be achieved, thereby affecting microchip operation and, commensurately, impacting microchip manufacture by reducing yields and increasing costs. Densely-arranged PL gates and peripheral metal-oxide-semiconductor (MOS) gates suffer under this paradigm, particularly when processed simultaneously.
A need thus exists in the prior art for a method of forming PL gates that facilitates the fill-in of inter-layer dielectric material. A further need exists for a method of simultaneously etching densely arranged and peripheral semiconductor gates.